DocumentCode
1760013
Title
A New Selective Loop Bias Mapping Phase Disposition PWM With Dynamic Voltage Balance Capability for Modular Multilevel Converter
Author
Jun Mei ; Ke Shen ; Bailu Xiao ; Tolbert, Leon M. ; Jianyong Zheng
Author_Institution
Jiangsu Provincial Key Lab. of Smart Grid Technol. & Equip., Southeast Univ., Nanjing, China
Volume
61
Issue
2
fYear
2014
fDate
Feb. 2014
Firstpage
798
Lastpage
807
Abstract
This paper presents an improved phase disposition pulsewidth modulation (PWM) (PDPWM) for the modular multilevel converter (MMC) which is based on the selective loop bias mapping (SLBM) method. Its main idea is to change the bias of the PDPWM carrier wave cycling according to the balance situation of the system. This new modulation method can operate at symmetric condition to generate an output voltage with as many as 2N + 1 levels, and by SLBM, the voltages of the upper/lower arm capacitors can be well balanced. Compared to carrier phase-shifted PWM, this method is more easily to be realized and has much stronger dynamic regulation ability. Specially, this method has no issues of sorting, which makes it suitable for MMC with a large number of submodules in one leg. With simulation and experiments, the validity of the proposed method has been shown.
Keywords
PWM power convertors; MMC; PDPWM carrier wave cycling; SLBM; dynamic voltage balance capability; modular multilevel converter; output voltage generation; selective loop bias mapping phase disposition pulsewidth modulation; Capacitors; Indexes; Phase modulation; Pulse width modulation; Sorting; Voltage control; Dynamic voltage balance; modular multilevel converter (MMC); phase disposition (PD) pulsewidth modulation (PWM) (PDPWM); selective loop bias mapping (LBM) (SLBM);
fLanguage
English
Journal_Title
Industrial Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0278-0046
Type
jour
DOI
10.1109/TIE.2013.2253069
Filename
6480872
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