DocumentCode
1760954
Title
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC
Author
Shi-Yu Huang ; Jeo-Yen Lee ; Kun-Han Tsai ; Wu-Tung Cheng
Author_Institution
Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
33
Issue
8
fYear
2014
fDate
Aug. 2014
Firstpage
1258
Lastpage
1268
Abstract
In this paper, we present a general at-speed test method for die-to-die interconnects and demonstrate its particular application to the interposer wires in a 2.5-D IC. At the heart of this method is a pulse-vanishing test technique (called PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the driver end. If this pulse vanishes at the receiver´s output, then it indicates the presence of a delay fault. This PV-test technique is effective for detecting not only resistive open faults, but also resistive bridging faults between interposer wires. This method has several other advantages. For example, the implementation is especially easy as it incorporates only logic cells and can be merged with boundary scan cells. Also, it can support on-the-spot diagnosis which is desirable in applications where subsequent built-in self-repair is needed.
Keywords
boundary scan testing; integrated circuit interconnections; integrated circuit testing; wires (electric); 2.5-D IC; at speed test method; die to die interconnects; interposer wires; pulse vanishing test; wire under test; Circuit faults; Clocks; Delays; Integrated circuit interconnections; Wires; 25-D stacked IC; at-speed test; bridging fault; delay fault; die-to-die interconnect test; interposer; pulse-vanishing test;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2014.2316093
Filename
6856314
Link To Document