Two phase clocking subthreshold adiabatic logic

Our previously proposed ultra low-power subthreshold adiabatic logic has been a problem that noise margin is reduced, so that it is impossible to implement a cascade connection. In this paper, we propose a novel sub-threshold adiabatic logic. To evaluate our proposed circuit, a half adder, full adder, dynamic flip flop and 4×4 array multiplier are designed, and then the operation function and power dissipation are confirmed. From the simulation results, the power dissipation of the proposed multiplier is lower than that of the conventional CMOS.