A time-domain based multi-bit ADC for application in Delta-Sigma modulators

This paper presents an approach to the implementation of a time-domain based multi-bit quantizer, i.e., the input signal dependent propagation delay of a comparator becomes quantized by means of delay lines. The approach is best applied to Delta-Sigma modulators with a scaled quantizer where the input voltage range of the quantizer is typically limited to half the supply voltage. Different voltage levels can thus be well distinguished. In this application, the capacitive load of the loop-filter will be reduced to that of a single-bit quantizer as only one comparator needs to be connected to its output. Moreover, the approach benefits from shrinking transistor dimensions since the minimum delay of a delay line decreases whereby the resolution in time increases. Post-layout simulations of the quantizer embedded in a Verilog-A model of a third-order Delta-Sigma modulator prove the feasibility of the proposed approach.