Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling

Author

Ming-Long Fan ; Hu, Vita Pi-Ho ; Yin-Nien Chen ; Pin Su ; Ching-Te Chuang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

1-5 June 2014

Firstpage

1130

Lastpage

1133

Abstract

In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.

Keywords

SRAM chips; circuit optimisation; circuit simulation; integrated circuit layout; logic circuits; technology CAD (electronics); three-dimensional integrated circuits; 6T SRAM cells; NFET layer stacking; PFET tier; SRAM cell stability; TCAD mixed-mode simulations; design margins; dual reverse body biases; interlayer coupling; monolithic 3D logic circuit optimization; optimal layout; performance enhancements; planar 2D circuits; reduced interconnection length; Couplings; Delays; Inverters; Layout; SRAM cells; Three-dimensional displays; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865339

Filename

6865339