Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs

Author

Lin, G.J.Y. ; Hsu, C.B. ; Kuo, J.B.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2014

fDate

1-5 June 2014

Firstpage

1740

Lastpage

1743

Abstract

In this paper, a critical-path aware power consumption optimization (CAPCOM) using mixed-VTH cells for low-power SOC designs is presented. Using the critical-path weighted sensitivity as an index for assigning each cell to LVT, HVT or MVT, the CAPCOM provides an effective power saving for a low-volt/ low-power SOC design, as indicated in a 16-bit multiplier circuit with 3811 logic cells using a 90nm CMOS technology at 1V with a 44.9% reduction in power consumption as compared to the MVTCMOS technique using all-LVT cells.

Keywords

CMOS logic circuits; integrated circuit design; system-on-chip; CAPCOM; CMOS technology; HVT; MVTCMOS technique; all-LVT cells; critical-path aware power consumption optimization methodology; critical-path weighted sensitivity; logic cells; low-volt low-power SOC design; mixed threshold voltage cells; multiplier circuit; size 90 nm; voltage 1 V; CMOS integrated circuits; Delays; Optimization; Power demand; Sensitivity; Silicon; System-on-chip; MVTCMOS; SOC; algorithm; circuit optimization; design methodology; dual threshold; mixed threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865491

Filename

6865491