PSRR enhancement based on QFG techniques for low-voltage low-power design

Author

Valero, M.R. ; Ramirez-Angulo, Jaime ; Medrano, N. ; Celma, S.

Author_Institution

Group of Electron. Design - I3A, Univ. of Zaragoza, Zaragoza, Spain

fYear

2014

fDate

1-5 June 2014

Firstpage

2684

Lastpage

2687

Abstract

A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry and no additional power dissipation or supply requirements. Simulation and experimental verification of these characteristics is provided.

Keywords

MOSFET; analogue integrated circuits; low-power electronics; AC noise; LVLP DC circuits; PSRR enhancement technique; QFG techniques; biasing circuits; low voltage power low power DC circuits; power supply rejection ratio enhancement technique; supply rails; total internal noise; Educational institutions; Integrated circuit modeling; Logic gates; Noise; Rails; Semiconductor device modeling; Transistors; Analog integrated circuits; CMOS integrated circuits; low-voltage low power design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865726

Filename

6865726