DocumentCode
177297
Title
EOLE: Paving the way for an effective implementation of value prediction
Author
Perais, Arthur ; Seznec, Andre
Author_Institution
IRISA, INRIA, Rennes, France
fYear
2014
fDate
14-18 June 2014
Firstpage
481
Lastpage
492
Abstract
Even in the multicore era, there is a continuous demand to increase the performance of single-threaded applications. However, the conventional path of increasing both issue width and instruction window size inevitably leads to the power wall. Value prediction (VP) was proposed in the mid 90´s as an alternative path to further enhance the performance of wide-issue superscalar processors. Still, it was considered up to recently that a performance-effective implementation of Value Prediction would add tremendous complexity and power consumption in almost every stage of the pipeline.
Keywords
multiprocessing systems; power consumption; EOLE; multicore era; power consumption; single-threaded applications; superscalar processors; value prediction; Complexity theory; Engines; Out of order; Pipelines; Ports (Computers); Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on
Conference_Location
Minneapolis, MN
Print_ISBN
978-1-4799-4396-8
Type
conf
DOI
10.1109/ISCA.2014.6853205
Filename
6853205
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