An approach to design a matrix inversion hardware module using FPGA

This study work is basically aimed at designing and testing of hardware module to perform inversion operation of a matrix in a small time. Here, an approach is made for calculating 3×3 matrix inverse. There are many mathematical methods available for performing matrix inversion and out of them a suitable method, like Adjoint Matrix Method is selected by analysing the computational requirements. The mathematical method of calculating the inverse of matrix is then suitably converted into VHDL code. The code is then tested for simulation using a set of test matrices. After simulation is verified by checking the results of test inputs the code is tested for synthesizability. After the synthesizability is verified then it is finally tested for hardware verification by dumping into FPGA. Altera´s DE1 board which consists a Cyclone-II series FPGA EP2C20F484C7 FPGA is used for this study. The test inputs can be fed in either by using on board GPIO or UI or S RAM. The outputs are taken the same way either by GPIO or UI or written to S RAM and are then to be verified by comparing with actual results.