Low power look-up table topologies for FPGAs

We know that the demand for field programmable gate arrays (FPGAs) have been growing very rapidly over the past decade. The power dissipation is a major problem nowadays than speed and area. Currently, the leakage power dissipation is one of the most prominent drawback in the FPGA´s apart from dynamic power. This study includes the implementation of Look Up Table (LUT) using multiplexers and pass-transistors. A low power Multiplexer´s based on n-MOS transistors play an important role in FPGAs both in the routing blocks and in the configuration logic blocks (CLBs). The simulations are done using Microwind and Digital Schematic Electronic Computer Aided Design tools. In this study, a comparison is made with power among all the designs for 120 nm CMOS process technology.