Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm

In the paper we propose a novel architecture and implementation of 10-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-BD Double-sided (LBDD) algorithm has been used to calculate the DPWM signals of the 10-bit resolution hybrid DPWM for a Class-D digital audio amplifier. Noise-shaping process is used to support high fidelity with feasible values of time resolution. The proposed DPWM circuit is composed of two 6-bit counters and one Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay elements has been presented elsewhere [12]. The proposed 10-bit DPWM circuit, at switching frequency of 352.8 kHz, clock frequency of 45 MHz allows to attain SNR of 120 dB and THD of the output signal less than 0,1% within the audio baseband and modulation index of 0.98. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for one CMOS process are presented.