Efficient implementation for accurate analysis of CED circuits against multiple faults

Reliability issues became an important concern in deep submicron CMOS devices. Concurrent Error Detection (CED) scheme has been proved to be an efficient technique in such a context. Different efforts were reported to quantify the efficiency of CED schemes but generally they consider single faults or suppose that implemented checker mechanisms are fault-free. This paper describes an alternative solution for CED circuits analysis, where the whole circuit (including checker mechanisms) is supposed to be fault prone. The proposed approach is based on Probabilistic Transfer Matrices and then can deal with multiple faults. The time efficiency of the proposed solution is demonstrated through arithmetic circuits.