DocumentCode
1777149
Title
Characteristics of In0.17 Al0.83 N/AlN/GaN MOSHEMTs with steeper than 60 mV/decade sub-threshold slopes in the deep sub-threshold region
Author
Zongyang Hu ; Jana, Rittwik ; Meng Qi ; Ganguly, Shaumik ; Bo Song ; Kohn, Erhard ; Jena, D. ; Xing, Huili Grace
Author_Institution
Univ. of Notre Dame, Notre Dame, IN, USA
fYear
2014
fDate
22-25 June 2014
Firstpage
27
Lastpage
28
Abstract
Realization of steep sub-threshold slope (SS) transistors requires exploiting carrier transport mechanisms such as tunneling [1], and also alternative gate barrier materials (i.e. ferroelectric materials) with internal voltage gain [2]. Theoretical studies on piezoelectric barriers indicate that it is possible to achieve internal voltage amplification and steep SS in GaN MOSHEMTs by utilizing electrostriction in conjunction with piezoelectricity in AlN and InAlN [3] [4]. Less than 60 mV/decade SS was experimentally observed in GaN MOSHEMTs with InAlN barriers, in which the steep transition was tentatively correlated with the inhomogeneous distribution of polarization in the barrier [5]. However, steep SS were only observed at drain current (Id) near nA/mm regimes, which leads to difficulties in interpretation of experiment data. Understanding of the mechanism of the steep SS in these devices is still unclear and needs more characterization and modeling. In this work we demonstrate InAlN/AlN/GaN MOSHEMTs with less than 60 mV/decade SS in deep sub-threshold regions (1E-8 A/mm and below) at room temperature (RT). Drain voltage and temperature dependent characteristics are provided with analysis for advancing our understanding of this phenomenon.
Keywords
III-V semiconductors; aluminium compounds; gallium compounds; high electron mobility transistors; indium compounds; piezoelectricity; wide band gap semiconductors; In0.17Al0.83N-AlN-GaN; MOSHEMT characteristics; SS transistors; carrier transport mechanisms; deep sub-threshold region; drain current; drain voltage; electrostriction; gate barrier materials; inhomogeneous polarization distribution; internal voltage amplification; internal voltage gain; piezoelectric barriers; piezoelectricity; steep sub-threshold slope transistors; temperature 293 K to 298 K; temperature dependent characteristics; tunneling; Capacitance; Electrostriction; Gallium nitride; III-V semiconductor materials; Logic gates; Plasma temperature; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference (DRC), 2014 72nd Annual
Conference_Location
Santa Barbara, CA
Print_ISBN
978-1-4799-5405-6
Type
conf
DOI
10.1109/DRC.2014.6872283
Filename
6872283
Link To Document