Design of a low-power calibratable charge-redistribution SAR ADC

This paper describes the implementation of a calibratable charge-redistribution (CR) based successive-approximation-register (SAR) analog-to-digital converter (ADC). This differential 13-bit CR SAR ADC is implemented with a unit capacitance of 1.54 fF which is much smaller than the capacitance used in most novel SAR ADCs. As a result, the area and the power consumption are reduced significantly. In the targeted 65-nm technology with a supply voltage of 1.2V, an optimistic FOM of about 2.76 fJ/conversion-step is achieved through simulations. Since the larger mismatch between such small capacitors of the ADC degrades its linearity significantly, a foreground calibration technique based on trimming each capacitance with smaller switchable capacitors is developed to compensate the mismatch. Also, for the purpose of mismatch detection, an offset-calibratable double-tail latch comparator is designed to achieve an offset below 70 μV.