Double node charge sharing SEU tolerant latch design

Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing mechanisms among these nodes, are a great concern in nanometer SRAMs, since pairs of cells are influenced. The concern is also extended to SEU related soft error tolerant latch designs, where multiple memory elements are exploited. In this work, we deal with double node charge sharing SEUs (DNCS-SEUs) that affect latch operation and we propose a new latch topology that it is capable to provide soft error tolerance under these new circumstances where single nodes or pairs of nodes are influenced by an SEU. Simulation results validate the efficiency of the new design.