Improving the significance of probabilistic circuit fault emulations

Recent trends go into the direction to tolerate a certain number of faults in integrated circuits, at locations where the error remains unnoticed by the user, trying to further extend Moore´s law. In order to enable such an approach, a comprehensive analysis of the probabilistic behavior of the circuit is required. We focus on FPGA-based probability-aware circuit fault emulation in order to do this analysis. Faults are injected at run-time, based on error probabilities, into the circuit. The influence on the circuit outputs is observed by comparing the fault-free with the faulty circuit. The probability-awareness allows us to model, for instance, different voltage-domains or channel widths, within the same circuit. Previous work is usually restricted to a non-probabilistic treatment of circuit faults, due to its complexity in terms of resource requirements and the difficulty to generate statistical significant results. In this work we will present two fundamental strategies, in order to tackle this latter issue. First, we will present methods to separate the data and control path of the circuit. Errors can only be tolerated in the data path of a circuit. Hence, it is necessary to reliably identify the control path inside the netlist, in order to make it robust against faults. Consequently, the control path hast to be excluded from the emulations. Secondly, we will present algorithms to score the stability of the measured output error probability. We will present ways to determine how many clock cycles have to be emulated in order to get a stable simulation result. By applying those methods we are able to generate trustworthy information about the probabilistic behavior of a circuit.