A Low Power Test-per-Clock BIST Scheme through Selectively Activating Multi Two-Bit TRCs

A low power test-per-clock built-in self-test (BIST) scheme based on 2-bit TRC is presented in this paper. The low power during testing can be obtained by selectively activating multi 2-bit twisting ring counters (AM2B-TRC). The optimal number of activated 2-bit twisting ring counters is also explored in this paper. Experimental results based on ISCAS´85 benchmark circuits show that the proposed low power test-per-clock BIST scheme has the improved performance including power, fault coverage and test length, comparing with the corresponding already known low power test-per-clock BIST scheme. In addition, the advantage of the proposed low power test-per-clock BIST scheme can be used for testing more than one module in a system on a chip (SoC).