Modeling of through-silicon via´s (TSV) with a 3D planar integral equation solver

Author

Sercu, Jeannick ; Schwartzmann, Thierry

Author_Institution

EEsof EDA, Agilent Technol., Ghent, Belgium

fYear

2014

fDate

14-16 May 2014

Firstpage

1

Lastpage

4

Abstract

Through-silicon via (TSV) interconnection technology is seen as a key enabling technology for stacking silicon dies and building 3D chips. In this paper, we present a novel technique to enable the modeling of through-silicon via interconnects within a 3D planar integral equation solver. The technique is capable of modeling both the dielectric isolation effects of the TSV oxide and the metal-oxide-semiconductor (MOS) depletion effects at the TSV oxide - silicon bulk contact regions.

Keywords

integral equations; integrated circuit interconnections; integrated circuit modelling; isolation technology; silicon; three-dimensional integrated circuits; 3D chip building; 3D planar integral equation solver; MOS depletion effect; TSV interconnection; TSV oxide-silicon bulk contact region; dielectric isolation effect; key enabling technology; metal-oxide-semiconductor depletion effect; silicon die stacking; through-silicon via modeling; Capacitance; Coatings; Dielectrics; Mathematical model; Silicon; Three-dimensional displays; Through-silicon vias; 3D interconnects; 3D planar EM; TSV; integral equation; through-silicon via;

fLanguage

English

Publisher

ieee

Conference_Titel

Numerical Electromagnetic Modeling and Optimization for RF, Microwave, and Terahertz Applications (NEMO), 2014 International Conference on

Conference_Location

Pavia

Type

conf

DOI

10.1109/NEMO.2014.6995659

Filename

6995659