Hardware implementation for a new design of the VBSME Used in H.264/AVC

Motion estimation (ME) in video coding standard H.264/AVC adopts variable block size (VBSME) which provides high compression rates but requires much higher computation compared to the previous coding standards. To overcome this complexity, this paper describes a VHDL design and an implementation of VBSME. The design is based on partitioning each 16×16 macroblock into sixteen 4×4 non overlapping subblocks. The motion estimation of these subblocks is performed in parallel in order to use them to form the 41 subblocks of different sizes specified by the standard. As a result, this new design has in consideration low latency and high throughput with a maximum frequency which reaches over than 277 MHz on a Xilinx-Vittex5-LX110T FPGA.