DocumentCode
1783222
Title
Remote Invalidation: Optimizing the Critical Path of Memory Transactions
Author
Hassan, Asif ; Palmieri, Roberto ; Ravindran, Binoy
Author_Institution
Electr. & Comput. Eng. Dept., Virginia Tech, Blacksburg, VA, USA
fYear
2014
fDate
19-23 May 2014
Firstpage
187
Lastpage
197
Abstract
Software Transactional Memory (STM) systems are increasingly emerging as a promising alternative to traditional locking algorithms for implementing generic concurrent applications. To achieve generality, STM systems incur overheads to the normal sequential execution path, including those due to spin locking, validation (or invalidation), and commit/abort routines. We propose a new STM algorithm called Remote Invalidation (or RInval) that reduces these overheads and improves STM performance. RInval´s main idea is to execute commit and invalidation routines on remote server threads that run on dedicated cores, and use cache-aligned communication between application´s transactional threads and the server routines. By remote execution of commit and invalidation routines and cache-aligned communication, RInval reduces the overhead of spin locking and cache misses on shared locks. By running commit and invalidation on separate cores, they become independent of each other, increasing commit concurrency. We implemented RInval in the Rochester STM framework. Our experimental studies on micro-benchmarks and the STAMP benchmark reveal that RInval outperforms InvalSTM, the corresponding non-remote invalidation algorithm, by as much as an order of magnitude. Additionally, RInval obtains competitive performance to validation-based STM algorithms such as NOrec, yielding up to 2x performance improvement.
Keywords
cache storage; concurrency control; multi-threading; software performance evaluation; RInval; Rochester STM framework; STAMP benchmark; STM performance improvement; cache-aligned communication; commit concurrency; commit routines; concurrent applications; critical path optimization; invalidation routines; memory transactions; microbenchmarks; overhead reduction; remote execution; remote invalidation; remote server threads; sequential execution path; software transactional memory systems; spin locking; transactional threads; validation-based STM algorithms; Benchmark testing; Concurrent computing; Hardware; Instruction sets; Scalability; Servers; Synchronization; Remote Invalidation; Software Transactional Memory; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2014 IEEE 28th International
Conference_Location
Phoenix, AZ
ISSN
1530-2075
Print_ISBN
978-1-4799-3799-8
Type
conf
DOI
10.1109/IPDPS.2014.30
Filename
6877254
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