Soft error mitigation through selection of noninvert implication paths

As transistor feature size scales down, soft errors in combinational logic because of high-energy particle radiation is gaining increasing concerns. In this paper, a soft error mitigation method based on accurate mathematical modeling of SER and addition of non-invert functionally redundant wires (FRWs) is proposed. In the proposed method, the factors which have significant influences on SER because of addition of FRWs are modeled to evaluate the change of SER without any simulations. Non-invert FRWs are explored and selected over previous invert FRWs to achieve the same masking effects due to the low SET probability and low overhead of non-invert wires. Experiment results on ISCAS´89 benchmark circuits show that our proposed soft error mitigation method can achieve 19.73% SER reduction at the expense of 4.57% hardware, 3.24% power, and 3.81% delay overhead on average.