DocumentCode
1787757
Title
Multithreaded pipeline synthesis for data-parallel kernels
Author
Mingxing Tan ; Bin Liu ; Dai, Shaotao ; Zhiru Zhang
Author_Institution
Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
fYear
2014
fDate
2-6 Nov. 2014
Firstpage
718
Lastpage
725
Abstract
Pipelining is an important technique in high-level synthesis, which overlaps the execution of successive loop iterations or threads to achieve high throughput for loop/function kernels. Since existing pipelining techniques typically enforce in-order thread execution, a variable-latency operation in one thread would block all subsequent threads, resulting in considerable performance degradation. In this paper, we propose a multithreaded pipelining approach that enables context switching to allow out-of-order thread execution for data-parallel kernels. To ensure that the synthesized pipeline is complexity effective, we further propose efficient scheduling algorithms for minimizing the hardware overhead associated with context management. Experimental results show that our proposed techniques can significantly improve the effective pipeline throughput over conventional approaches while conserving hardware resources.
Keywords
multi-threading; pipeline processing; processor scheduling; context management; context switching; data-parallel kernels; hardware overhead; hardware resources; high-level synthesis; in-order thread execution; loop iterations; loop/function kernels; multithreaded pipeline synthesis; out-of-order thread execution; pipeline throughput; pipelining techniques; scheduling algorithms; variable-latency operation; Context; Instruction sets; Kernel; Pipeline processing; Schedules; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2014 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
Type
conf
DOI
10.1109/ICCAD.2014.7001431
Filename
7001431
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