Buffer reduction algorithm for mesh-based clock distribution

In deep sub-micron technology, Mesh-based clock distribution is becoming a preferred method to distribute the clock since it is tolerant to process variations. Buffers are placed on the mesh nodes to drive the mesh wire capacitance and large load capacitance of clock sinks. In this short paper, we propose a buffer reduction algorithm which can reduce the power dissipated in clock meshes. We calculate the importance of each buffer by the impact its removal has on the clock latency and clock slew at sinks. We then calculate a rank for each buffer and buffers with lower ranks are removed. Our buffer reduction algorithm is able to achieve 15-18% reduction in power at the cost of 10-20 ps increase in skew when compared to the previously published work.