VLSI architectures for Givens Rotation based RLS lattice ladder FIR filter algorithms using circular buffer technique

This paper presents the most efficient VLSI architecture for LS lattice ladder FIR filter. The algorithm used here is Givens Rotation wherein the computational complexity(operations per time update) is reduced from O(M²) to just O(M). This algorithm tries to adapt a very low power interface on itself and occupies a smaller surface square unit of area for its VLSI implementation. At first the hardware architecture for the error updating RLS feedback algorithm and the coefficient performance units is described. Secondly, one such architecture for Givens RLS lattice ladder stage and is processor array logic is described. This entire description is implemented on Virtex-5 FPGA(XUPV5LX110T) using VHDL. This implementation achieved the best results for which it occupied only 1075 slice registers(1% utilization of total slice registers on the board), 876 LUT´s(1%) giving the extreme throughput performance on the design. The implementation makes use of circular buffers to update the Dual Port Memory, RAM. This showed a 68.75% increase in the performance as compared to a normal efficient VLSI architecture design.