DocumentCode
1789165
Title
Comparative analysis of different optimization technique for Sobel edge detection on FPGA
Author
Lavanya, K.B. ; Ramana Reddy, K.V. ; Yellampalli, Siva S.
Author_Institution
VLSI Design & Embedded Syst., UTL Technol., Bangalore, India
fYear
2014
fDate
10-11 Oct. 2014
Firstpage
1
Lastpage
5
Abstract
In this paper we preset implementation of an optimized Sobel edge detection algorithm on FPGA. The optimized gradient based edge detection method reduces the area up to 48.76% compared to existing gradient calculation unit, and also reduces propagation delay up to 51% compared to the area optimized architecture. The entire project is implemented on Spatran-3E FPGA board. VGA interface is used to display the edge detection image on the monitor.
Keywords
edge detection; field programmable gate arrays; optimisation; FPGA; Spatran-3E FPGA board; VGA interface; optimization technique; optimized Sobel edge detection algorithm; optimized gradient based edge detection method; Computer architecture; Delays; Detectors; Field programmable gate arrays; Image edge detection; Monitoring; Simulation; Block Memory; FPGA; Sobel edge detector;
fLanguage
English
Publisher
ieee
Conference_Titel
Advances in Electronics, Computers and Communications (ICAECC), 2014 International Conference on
Conference_Location
Bangalore
Type
conf
DOI
10.1109/ICAECC.2014.7002485
Filename
7002485
Link To Document