Integration of III–V materials and Si-CMOS through double layer transfer process

Author

Kwang Hong Lee ; Shuyu Bao ; Fitzgerald, Emma ; Chuan Seng Tan

Author_Institution

Singapore-MIT Alliance for Res. & Technol. (SMART), Singapore, Singapore

fYear

2014

fDate

15-16 July 2014

Firstpage

32

Lastpage

32

Abstract

A method to integrate III-V compound semiconductor and SOI-CMOS on Si substrate is demonstrated. The SOI-CMOS layer is temporarily transferred on a Si handle wafer. Another III-V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Finally, the handle wafer is released to realize the SOI-CMOS on III-V/Si substrate. Through this method, high temperature III-V materials growth can be completed without the presence of the CMOS layer, hence damage to the CMOS layer is avoided.

Keywords

CMOS integrated circuits; III-V semiconductors; elemental semiconductors; integrated circuit interconnections; silicon; silicon-on-insulator; three-dimensional integrated circuits; wafer bonding; III-V compound semiconductor; SOI-CMOS; Si; double layer transfer process; fusion bonding; high temperature III-V materials growth; silicon substrate; wafer bonding; Bonding; CMOS integrated circuits; Gallium nitride; Silicon; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Temperature Bonding for 3D Integration (LTB-3D), 2014 4th IEEE International Workshop on

Conference_Location

Tokyo

Print_ISBN

978-1-4799-5260-1

Type

conf

DOI

10.1109/LTB-3D.2014.6886171

Filename

6886171