Introduction to the special session on “Silicon photonic interconnects: an illusion or a realistic solution?”

The performance of a multiprocessor system-on-chip (MPSoC) is determined not only by the performance of its processing cores and memories, but also by how efficiently they collaborate with one another. It is the MPSoCs communication architecture which determines the collaboration efficiency. The migration towards MPSoCs is propelled by the shrinking feature sizes in each generation of process technology. On the one hand, smaller transistors allow for more processor cores and memories on a single chip and result in more on-chip computations as well as communications. On the other hand, reducing feature sizes makes on-chip communication more difficult. The International Roadmap for Semiconductors (ITRS) shows that the latency of metallic interconnects increases exponentially as feature sizes decrease. On-chip communication using metallic interconnects will need more than one clock cycle to send information from sources to destinations. Moreover, metallic interconnects consume a significant amount of power. Studies shows that global metallic interconnects could consume kilowatts of power to achieve required communication bandwidth by 2020 [1].