DocumentCode
1797049
Title
A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting
Author
Yuan-Fu Lin ; Chang-Cheng Huang ; Lee, Jiunn-Yih Max ; Chih-Tien Chang ; Shen-Iuan Liu
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2014
fDate
10-12 Nov. 2014
Firstpage
273
Lastpage
276
Abstract
A 5-20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10-12 over a 5m cable.
Keywords
CMOS integrated circuits; adaptive equalisers; clocks; error statistics; BER; CMOS technology; CTLE; asynchronous clock; bit error rates; bit rate 5 Gbit/s to 20 Gbit/s; edge counting technique; power efficiency improvement; power scalable adaptive continuous-time linear equalizer; size 40 nm; Adaptive equalizers; CMOS integrated circuits; Semiconductor device measurement; Solid state circuits; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location
KaoHsiung
Print_ISBN
978-1-4799-4090-5
Type
conf
DOI
10.1109/ASSCC.2014.7008913
Filename
7008913
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