Power efficient data rate for photonic interposer

Author

Chujo, Norio ; Uematsu, Yutaka ; Yasunaga, Moritoshi

Author_Institution

Yokohama Res. Lab., Hitachi, Ltd., Yokohama, Japan

fYear

2014

fDate

4-6 Nov. 2014

Firstpage

23

Lastpage

26

Abstract

We describe a chip-to-chip interconnect solution that will enable 40-Tb/s bandwidth per apparatus and 10-Tb/s bandwidth per LSI in 2020. By using an interposer which can increase wiring density, we aim to increase the parallel number of data, relax the data rate, and integrate optical transceivers in the package. Doing so both enhances bandwidth and reduces power consumption. By analyzing the optical interconnect composed of a Si interposer, VCSEL, and PD, we determine that about 10Gb/s is the most power efficient data rate.

Keywords

elemental semiconductors; integrated circuit interconnections; integrated circuit packaging; integrated optoelectronics; large scale integration; optical transceivers; power consumption; silicon; surface emitting lasers; LSI; Si; VCSEL; bit rate 10 Tbit/s; bit rate 40 Tbit/s; chip-to-chip interconnect; optical interconnect; optical transceivers; photonic interposer; power consumption; wiring density; Bandwidth; Large scale integration; Optical devices; Optical fibers; Optical interconnections; Vertical cavity surface emitting lasers; Wiring; Optical interconnect; chip-to-chip; interposer; power efficiency;

fLanguage

English

Publisher

ieee

Conference_Titel

CPMT Symposium Japan (ICSJ), 2014 IEEE

Conference_Location

Kyoto

Print_ISBN

978-1-4799-6194-8

Type

conf

DOI

10.1109/ICSJ.2014.7009600

Filename

7009600