Flexible hardware architecture of SEFDM transmitters with real-time non-orthogonal adjustment

Field Programmable Gate Arrays (FPGA) offer a unique combination of software abstraction and hardware performance, enabled by programming languages such as VHDL or Verilog. Inherent from this capability is a multitude of different design possibilities for a single implementation problem. A system can be designed which allows for real world evaluation at real time speeds of algorithms ordinarily restricted to simulation environments. Presented here is an FPGA implementation of a method of generating non-orthogonal Frequency Division Multiplexed signals, where the spacing between sub-carriers can be controlled externally without the need for re-synthesis. The internal data-paths and associated algorithms are constructed so as to react to changes which dictate the aforementioned spacing, and as such represents a dynamic transmission platform for research purposes.