DocumentCode
1801024
Title
Test structure generation to quantify filling impact
Author
Remy, Laurent ; Portal, Jean-Michel ; Coll, Philippe ; Picot, Fabrice ; Mico, Philippe
Author_Institution
ZI Rousset, ATMEL Rousset, Rousset
fYear
2008
fDate
25-27 March 2008
Firstpage
1
Lastpage
5
Abstract
In present and future technology nodes, the insertion of metal filling can lead to timing yield losses. In this paper, we present a test structure generation method to study the impact of metal filling on interconnect timings. Such a method is mandatory when dealing with metal filling, because its insertion in real design does not follow standardized rules. The proposed test structure generation method is based on design of experiment (DOE) to minimize the number of structures. The DOE approach links test structures timings to filling pattern characteristics. This timing model is first validated by comparison with the test structures electrical simulations. Then the model is used for statistical analysis about filling impact depending on metal level.
Keywords
design of experiments; integrated circuit interconnections; integrated circuit testing; design of experiment; filling impact; filling pattern; future technology nodes; interconnect timings; metal filling; statistical analysis; test structure generation; test structures electrical simulations; timing yield losses; Capacitance; Filling; Planarization; Ring oscillators; Semiconductor device modeling; Shape; Statistical analysis; Testing; Timing; US Department of Energy; Capacitance; Design of Experiment; Dispersion; Interconnect; Metal filling; Modelization; Ring Oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on
Conference_Location
Tozeur
Print_ISBN
978-1-4244-1576-2
Electronic_ISBN
978-1-4244-1577-9
Type
conf
DOI
10.1109/DTIS.2008.4540252
Filename
4540252
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