An all-digital phase-locked loop for high-speed clock generation

Author

Chung, Ching-Che ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

3

fYear

2002

fDate

2002

Firstpage

679

Lastpage

682

Abstract

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35 μm 1P4M CMOS process can operate from 40 MHz to 540 MHz. The p-p jitter of the output clock is less than ±170 ps, and the rms jitter of the output clock is less than 39 ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications

Keywords

CMOS digital integrated circuits; clocks; digital phase locked loops; timing jitter; 0.35 μm 1P4M CMOS; 0.35 micron; 40 MHz to 540 MHz; 40 to 540 MHz; ADPLL architecture; SoC applications; all-digital phase-locked loop; design complexity; high-speed clock generation; jitter below 39 ps; rms jitter; standard cell library; system-on-chip applications; CMOS process; Circuits; Clocks; Filters; Frequency conversion; Jitter; Libraries; Phase frequency detector; Phase locked loops; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010315

Filename

1010315