Pixel-and-column pipeline architecture for FFT-based image processor

Author

Morikawa, Makoto ; Katsumata, Atsushi ; Kobayashi, Koji

Author_Institution

Res. & Dev. Headquarters, Yamatake Corp., Kanagawa, Japan

Volume

3

fYear

2002

fDate

2002

Firstpage

687

Lastpage

690

Abstract

Fast Fourier Transform based image-processing algorithms, such as Phase-Only Correlation, and Fourier-Mellin Transform are known to be time-consuming, but they are becoming more popular by the benefit of advances in the area of semiconductor technology. These algorithms need a series of pre-processing and postprocessing to the main processing of FFT. A pixel-and-column pipeline architecture, that has two-layered pipeline for a pixel and a column, is proposed. An LSI that provides those algorithms at the real-time response is designed based on the architecture. The processing time of 256×256 POC is 10.06 ms, and 2.57 times faster than the previous implementation

Keywords

CMOS digital integrated circuits; digital signal processing chips; fast Fourier transforms; image processing equipment; large scale integration; pipeline processing; 10.06 ms; 256 pixel; 65536 pixel; FFT; Fast Fourier Transform; Fourier Mellin Transform; LSI; image-processing algorithms; phase-only correlation; pixel-and column pipeline architecture; postprocessing; pre-processing; processing time 10.06 ms; real-time; semiconductor technology; two-layered pipeline; Algorithm design and analysis; Computer architecture; Computer interfaces; Fast Fourier transforms; Large scale integration; Pipelines; Pixel; Random access memory; Spatial filters; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010317

Filename

1010317