Implementation of a testing environment for digital IP cores

This paper proposes a Verilog HDL-based fault simulation and testing environment for embedded IP core-based digital systems, specifically targeted towards synchronous memory-based systems, for detecting single stuck-line faults. The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a MUT (module under test) and the output streams from the MUT are fed into a response data analyzer. A fault is detected if the module response is different from that of the fault-free module. All of the faults detected are recorded in a detailed simulation results file. The fault simulator is suitable for testing sequential circuits described in Verilog HDL. The automatic fault simulator generates tests for the MUT described at the gate and flip-flop level. There are very few constraints on the circuit. The simulation process is completely automatic, and requires no intervention from the designer during the test generation process. The paper describes in detail the architecture and applications of the fault simulator along with the models of sequential elements used. Results on some simulation experiments on ISCAS 89 sequential benchmark circuits are also provided.