Timing requirement for reliable latch-based circuit design

Author

Lee, Young Jun ; Kim, Yong-Bin ; Lombardi, E. ; Park, Nohpill

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

Volume

2

fYear

2004

fDate

18-20 May 2004

Firstpage

1519

Abstract

This paper presents a framework of simulation and verification methodology for latch-based VLSI design. The proposed methodology includes optimal latch insertion point identification, how to consider clock skew for timing, and how to simulate circuits to verify the timing and functionality considering the clock skew in high speed VLSI systems for latch-based design. An existing flip-flop based FFT block is converted to latch-based design using the proposed methodology, and the performance of the block is increased by 10%.

Keywords

VLSI; circuit simulation; fast Fourier transforms; flip-flops; integrated circuit design; logic design; logic simulation; timing; VLSI design; clock skew; flip-flop based FFT block; latch-based circuit design; optimal latch insertion point identification; timing requirements; verification methodology; Circuit simulation; Circuit synthesis; Clocks; Delay effects; Design methodology; Integrated circuit interconnections; Latches; Logic; Region 1; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE

ISSN

1091-5281

Print_ISBN

0-7803-8248-X

Type

conf

DOI

10.1109/IMTC.2004.1351354

Filename

1351354