Parameter optimization tool for enhancing on-chip network performance

Author

Riihimäki, Jouni ; Salminen, Emo ; Kuusilinna, Kimmo ; Hämäläinen, Timo

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland

Volume

4

fYear

2002

fDate

2002

Abstract

In this paper, we present a tool to be used in the optimization of interconnection parameters in order to achieve optimal performance and implementation with minimal costs. The optimization tool uses an iterative algorithm to optimize the interconnection parameters, such as data width, priorities, and the time an agent can reserve the interconnection, to fulfill the given constraints. In the used test case, the required area decreased 50% while 85% of the original bandwidth was obtained. This was due to an improved arbitration process.

Keywords

circuit CAD; circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; iterative methods; software tools; agent interconnection reservation time; arbitration process; data width; interconnection bandwidth; interconnection constraints; interconnection parameters; interconnection priorities; interconnection test; iterative algorithm; minimal costs; on-chip network performance enhancement; optimal implementation; optimal performance; parameter optimization; Bandwidth; Complex networks; Constraint optimization; Cost function; Digital systems; Iterative algorithms; Network-on-a-chip; Optimization methods; System-on-a-chip; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010388

Filename

1010388