DocumentCode
1804610
Title
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
Author
Plouchart, J.-O. ; Ferriss, M. ; Natarajan, A. ; Valdes-Garcia, A. ; Sadhu, B. ; Rylyakov, A. ; Parker, B. ; Beakes, M. ; Babakani, A. ; Yaldiz, S. ; Pileggi, L. ; Harjani, R. ; Reynolds, S. ; Tierno, J.A. ; Friedman, D.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2012
fDate
9-12 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.
Keywords
CMOS integrated circuits; circuit noise; circuit tuning; jitter; phase locked loops; power consumption; silicon-on-insulator; voltage-controlled oscillators; SOI-CMOS PLL; adaptive biasing; adaptively biased VCO; frequency 23.5 GHz; frequency tuning; jitter; power 24 mW; power 34 mW; power consumption; size 32 nm; Current measurement; Frequency measurement; Jitter; Phase locked loops; Phase noise; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4673-1555-5
Electronic_ISBN
0886-5930
Type
conf
DOI
10.1109/CICC.2012.6330593
Filename
6330593
Link To Document