An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications

Author

Abdollahi, S.R. ; Kiaei, S. ; Bakkaloglu, B. ; Fakhraie, S.M. ; Anvari, R. ; Abdollahi, S.E.

Author_Institution

Tehran Univ., Iran

Volume

4

fYear

2002

fDate

2002

Abstract

A programmable digitally controlled oscillator (DCO) core is mapped on an Altera MAX9400 CPLD that can be used for clock recovery circuit of a 2.4-19.2 Kb/sec Gaussian Minimum Shift Keying (GMSK) demodulator. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. The linearity and phase noise of the DCO are analyzed at different oscillation frequencies. Thermal drift and power supply level sensitivity are characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on a deep-submicron process.

Keywords

CMOS logic circuits; application specific integrated circuits; demodulators; digital control; digital radio; field programmable gate arrays; minimum shift keying; phase noise; programmable logic devices; radiofrequency oscillators; synchronisation; transceivers; variable-frequency oscillators; 100 MHz to 1 GHz; 2.4 to 19.2 Kbit/s; ASIC implementation; Altera MAX9400 CPLD; GMSK demodulator; Gaussian minimum shift keying demodulator; clock recovery circuit; digital wireless transceivers; linearity; phase noise; power supply level sensitivity; programmable digitally controlled oscillator core; thermal drift; Circuits; Clocks; Demodulation; Digital control; Frequency; GSM; Linearity; Oscillators; Transceivers; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010399

Filename

1010399