• DocumentCode
    1805060
  • Title

    A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS

  • Author

    Plouchart, J.-O. ; Sanduleanu, M.A.T. ; Toprak-Deniz, Z. ; Beukema, T.J. ; Reynolds, S. ; Parker, B.D. ; Beakes, M. ; Tierno, J.A. ; Friedman, D.

  • Author_Institution
    IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    2012
  • fDate
    9-12 Sept. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm2.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; power consumption; silicon-on-insulator; ENOB two-step subranging ADC; FOM; IIP3; SOI-CMOS technology; bit rate 3.2 Gbit/s; frequency 1.6 GHz; power 22 mW; power consumption; size 45 nm; voltage 1.05 V; CMOS integrated circuits; Calibration; Clocks; FETs; History; Latches; Semiconductor device measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2012 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4673-1555-5
  • Electronic_ISBN
    0886-5930
  • Type

    conf

  • DOI
    10.1109/CICC.2012.6330610
  • Filename
    6330610
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1805060