Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.