Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC

To improve the computation precision of the beams control system in a heavy ion accelerator system, a floating-point phase and magnitude digital detector is proposed. The coordinate rotation digital computer (CORDIC) algorithm is utilized to compute results in digital form. Due to the hardware design simplicity, shifting and adding operations become two main operators to perform the computation. The proposed CORDIC core is based on floating-point arithmetic units to obtain high accuracy for the closed-loop control system. A Pipeline-based architecture is applied instead of CORIDC´s iteration process in order to maximize computation performance. Moreover, comparison of hardware 8-and 16-stage pipeline-based simulations with Matlab/simulink is statically analysis to differentiate the accuracy of the two hardware architectures. Finally, resource efficiencies based on target Xilinx FPGA xc5vlx110 and 130-nm Silicon technology are shown that 8-and 16-stage hardwares consume maximum 18% and 38% of total slices at 134 MHz on the target FPGA, as well as 43,164 um and 83,769 um at 617 MHz on Silicon technology.