VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design

This paper describes a VHDL modeling environment of built-in-self-test (BIST) for system on chip (SOC) testing to ease the description, verification, simulation and hardware realization. The VHDL model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. Once detecting the particular approaches for input, output, main block and different modules, the VHDL descriptions are run through a VHDL simulator, which demonstrate the effectiveness of the model.