DocumentCode
1807872
Title
A 10–67-GHz CMOS step attenuator with improved flatness and large attenuation range
Author
Juseok Bae ; Jaeyoung Lee ; Cam Nguyen
Author_Institution
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
fYear
2013
fDate
21-23 Jan. 2013
Firstpage
78
Lastpage
80
Abstract
A four-bit CMOS step attenuator is designed using a new design method to achieve improved flatness and large attenuation range from 10-67 GHz. The design method is based on the frequency-response characteristics of the conventional Pi-, T-, and distributed attenuators. Over 10-67 GHz, the measured results exhibit attenuation flatness of 6.8 dB and attenuation range of 32-42 dB.
Keywords
CMOS integrated circuits; attenuators; field effect MMIC; CMOS step attenuator; distributed attenuators; four-bit CMOS step attenuator; frequency 10 GHz to 67 GHz; frequency-response characteristics; improved flatness; word length 4 bit; Attenuation; Attenuation measurement; Attenuators; CMOS integrated circuits; Design methodology; Transistors; Transmission line measurements; Attenuator; Pi-attenuator; RFIC; T-attenuator; distributed attenuator;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on
Conference_Location
Austin, TX
Print_ISBN
978-1-4673-1552-4
Electronic_ISBN
978-1-4673-1551-7
Type
conf
DOI
10.1109/SiRF.2013.6489438
Filename
6489438
Link To Document