Predicting IC Defect Level Using Diagnosis

Predicting defect level (DL) using fault coverage is an extremely difficult task but if can be accomplished ensures high quality while controlling test cost. Because IC testing now involves generating and combining tests from multiple fault models, it is important to understand how the coverage from each fault model relates to the overall DL. In this work, a new model is proposed which learns the effectiveness of fault models from the diagnostic results of defective chips, and predicts defect level using the derived measures of effectiveness and fault coverages of multiple fault models. The model is verified using fail data from an IBM ASIC and virtual fail data created through simulation. Experiment results demonstrate that this new model can predict DL more reliably than conventional approaches.