VLSI-array architecture for the hierarchical BMA

A VLSI-array architecture for the hierarchical block-matching algorithm (HBMA) using a mean pyramid structure is presented. Due to the novel arrangement of data flow, we can map the HBMA onto a systolic array without hardware redundancy. The architecture can estimate the motion vectors of a 720×480 pixels image with frame rate of 30, for the displacement of ±28 pixels, at 50 MHz clock rate. We simulated the proposed architecture using Verilog-XL and synthesized it using Compass. Simulation results show that the architecture can be fabricated with the state-of-the-art CMOS technologies in one chip