A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADC

A 0.6-to-200MSPS speed reconfigurable 0.49pJ/conversion 10bit ADC is implemented in a 90nm digital CMOS process. The proposed technique configures the ADC architecture for optimal power at a specific speed, while maintaining constant biasing current for each stage. The principal advantage of this approach is that speed programming is effected on the architectural rather than the circuit level, obviating large bias-current variations inherent in conventional approaches. This ADC achieves the widest speed reconfigurable range with a competitive low power performance and Figure-of-Merit (FOM).