Modular and efficient architecture for H.263 video codec VLSI

Author

Lee, Sang-hee ; Kim, Myungjin ; Kim, Keun-Bae

Author_Institution

ImpressTek Co. Ltd., Daejeon, South Korea

Volume

5

fYear

2002

fDate

2002

Abstract

We present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on a modular and unified interface for internal hardware engines, and enables the pipelined operation while keeping enough flexibility to extend the functionality of the VLSI. The developed VLSI supports the H.263 video codec and the low-level protocol processing such as H.223 and H.245, and thus can be used for the complete ITU-T H.324 or 3GPP 3G-324M audiovisual processor with an external audio codec.

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; multimedia communication; pipeline processing; video codecs; 0.35 μm standard-cell CMOS technology; 0.35 micron; 3GPP 3G-324M audiovisual processor; H.263 video codec VLSI; ITU-T H.324 audiovisual processor; VLSI functionality; external audio codec; internal hardware engines; low-level protocol processing; modular efficient hardware architecture; modular unified interface; multimedia communication; pipelined operation; Decoding; Discrete cosine transforms; Engines; Hardware; Image converters; Microprogramming; Mobile communication; Protocols; Very large scale integration; Video codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010656

Filename

1010656