DocumentCode
1810875
Title
A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs
Author
Lu, Ping ; Andreani, Pietro ; Liscidini, Antonio
Author_Institution
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
fYear
2011
fDate
12-16 Sept. 2011
Firstpage
459
Lastpage
462
Abstract
Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.
Keywords
CMOS analogue integrated circuits; CMOS digital integrated circuits; delay lines; digital phase locked loops; radiofrequency integrated circuits; radiofrequency oscillators; CMOS GRO; CMOS gated-ring-oscillator; DPLL; Vernier TDC; Vernier time-to-digital converter; bandwidth 800 kHz; current 3 mA; current consumption; delay line; digital phase-locked loop; frequency 25 MHz; signal bandwidth; size 90 nm; voltage 1.2 V; Delay; Inverters; Noise; Phase frequency detector; Phase measurement; Quantization; Strontium;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location
Helsinki
ISSN
1930-8833
Print_ISBN
978-1-4577-0703-2
Electronic_ISBN
1930-8833
Type
conf
DOI
10.1109/ESSCIRC.2011.6045006
Filename
6045006
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