DocumentCode
1812282
Title
A 100 MHz FPGA based floating point adder
Author
Narasimhan, D. ; Fernandes, D. ; Raj, V.K. ; Dorenbosch, J. ; Bowden, M. ; Kapoor, V.S.
Author_Institution
Comput. Sci. Eng., Texas Univ., Arlington, TX, USA
fYear
1993
fDate
9-12 May 1993
Abstract
The authors present the design of a floating-point adder implemented on a FPGA (field programmable gate array) that operates at 100 MHz. High-speed submicron technology FPGAs with a large number of logic blocks, which increased routing facility, were combined with a well-partitioned design. This adder adds two 13-b numbers and is implemented as an 8-stage pipeline
Keywords
field programmable gate arrays; 100 MHz; 8-stage pipeline; ASIC; FPGA based; floating point adder; full custom chip; high-speed submicron technology; increased routing facility; logic blocks; well-partitioned design; Adders; Clocks; Computer science; Delay effects; Field programmable gate arrays; Laboratories; Logic; Pins; Pipelines; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590348
Filename
590348
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