DocumentCode
1812639
Title
A graph model for investigating memory consistency
Author
Hu, Weiwu
Author_Institution
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
fYear
1994
fDate
19-22 Dec 1994
Firstpage
516
Lastpage
523
Abstract
The complexity of a multiprocessor memory system grows with the endeavors people make to improve the performance. The pseudo and real execution graphs introduced here can formally describe the complex event ordering behavior of the multiprocessor memory system and to verify the correctness of a parallel program under a consistency model. A pseudo execution graph represents the programmer´s abstraction of an execution in which memory accesses are simple, atomic operations. A loop in the pseudo execution graph indicates an incorrect execution. A real execution graph represents the hardware designer´s abstraction of an execution in which each memory access is a causal sequence of events. A loop in the real execution graph indicates that this execution is impossible to occur. A program is correct if all loops in the pseudo execution graphs cause loops in the corresponding real execution graphs
Keywords
computational complexity; fault tolerant computing; shared memory systems; atomic operation; complex event ordering behavior; consistency model; graph model; memory consistency; multiprocessor memory system complexity; parallel program correctness; pseudo execution graph; real execution graph; Computers; Costs; Delay; Hardware; Parallel processing; Scalability;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Systems, 1994. International Conference on
Conference_Location
Hsinchu
Print_ISBN
0-8186-6555-6
Type
conf
DOI
10.1109/ICPADS.1994.590364
Filename
590364
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